As transistors are scaled to smaller dimensions there is a need for higher switching speeds. One solution to increase transistor speed is to strain the silicon in the channel. Adding a small amount of strain to the silicon lattice structure promotes higher electron and hole mobilities, which increase transistor drain current and device performance.
When the lattice is under tensile strain, its physical symmetry is broken, and with it the electronic symmetry. The lowest energy level of the conduction band is split, with two of the six original states dropping to a lower energy level and four rising to a higher energy level. This renders it more difficult for the electrons to be ‘scattered’ between the lowest energy states by a phonon, because there are only two states to occupy. Whenever electrons scatter, it randomizes their motion. Reducing scatter increases the average distance an electron can travel before it is knocked off course, increasing its average velocity in the conduction direction. Also, distorting the lattice through tensile strain can distort the electron-lattice interaction in a way that reduces the electron's effective mass, a measure of how much it will accelerate in a given field. As a result, electron transport properties like mobility and velocity are improved and channel drive current for a given device design is increased in a strained silicon channel, leading to improved transistor performance.
High tensile films have recently been introduced to the transistor device manufacturing process. For example, highly tensile silicon nitride capping layers have been used in NMOS structures to induce tensile strain in the NMOS channel region. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel. However, highly tensile silicon nitride capping layers are generally deposited using thermal CVD processes, which may consume too much of thermal budget for advanced transistor architectures. In addition, silicon nitride capping layers are not appropriate for use in PMOS structures where it is preferable to have compressive strain in the PMOS channel region.
Additionally, biaxial strained silicon may also be achieved through the deposition of Si and silicon germanium (SiGe) epilayers, but is a costly process. Moreover, strained Si on SiGe epilayers utilize thick, complex, and defect containing buried SiGe layers (such as graded buffer layers where the Ge content is increased from 0% up to the targeted Ge concentration, typically 20%) in order to provide a template for a relaxed SiGe layer of constant Ge content. This layer becomes a virtual substrate for the strained Si epitaxy of which Ge diffusion, strain relaxation, and creation and propagation of misfit and threading dislocations are only some of the limitations that prevent it from being flexible for strain engineering.
Accordingly, new transistor architectures and fabrication processes for generating and modulating channel strain are needed.